MOVDQA - Move Aligned Double Quadword

Description

Moves a double quadword from the source operand (second operand) to the destination operand (first operand). This instruction can be used to move a double quadword to and from an XMM register and a 128-bit memory location, or between two XMM registers. When the source or destination operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.

To move a double quadword to or from unaligned memory locations, use the MOVDQU instruction.

While executing in 16-bit addressing mode, a linear address for a 128-bit data access that overlaps the end of a 16-bit segment is not allowed and is defined as reserved behavior. A specific processor implementation may or may not generate a #GP exception in this situation, and the address that spans the end of the segment may or may not wrap around to the beginning of the segment.

Operation

DEST SRC;

Intel® C++ Compiler Intrinsic Equivalent

MOVDQA __m128i _mm_load_si128 ( __m128i *p) MOVDQA void _mm_store_si128 ( __m128i *p, __m128i a)

SIMD Floating-Point Exceptions

None.

Protected Mode Exceptions

#GP(0) - If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If memory operand is not aligned on a 16-byte boundary, regardless of segment.

#SS(0) - If a memory operand effective address is outside the SS segment limit.

#NM - If TS in CR0 is set.

Real-Address Mode Exceptions

#UD - If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE-2 is 0.

#PF(fault-code) - If a page fault occurs.

#GP(0) - If memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside of the effective address space from 0 to FFFFH.

#NM - If TS in CR0 is set.

#UD - If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE2 is 0.

Virtual-8086 Mode Exceptions

Same exceptions as in Real Address Mode.

#PF(fault-code) - For a page fault.